Various forms of large scale integrated circuits are now commonly designed with the aid of automatic programmed machines known as synthesizers or compilers. Such machines start from a high level specification of the function of, for example, a digital data processor which is to be synthesized, and proceed via various stages of minimization and optimization, usually with the aid of a library of standard cells or circuits to provide a netlist which is a detailed specification of an integrated circuit implementing, in the desired technical format, the original chosen function. Typically the circuits which are produced by such design methods comprise tens or hundreds of thousands of gates and other devices and are accordingly of a complexity far beyond the ability of a human designer to check the operation of the circuit correctly.
Much time and attention has been devoted to the generation of test vectors which will reliably diagnose faults in the finished circuit. The development of test vectors for purely combinatorial circuits is comparatively easy, but for sequential circuits has long been recognized as a difficult task.
Sequential circuits are of two types. The first type, commonly called sequential glue logic, comprises combinatorial logic blocks separated by temporal barriers, which may be of latches or flip-flops. There may be feedback loop all over the logic. A second type is represented by controllable sequencers which implement finite state machines. These controllers are commonly designed by machine synthesizers which produce very efficient circuits. The present invention is particularly concerned with the generation of test vectors from a specification of a finite state machine.